// Copyright (C) 1953-2022 NUDT
// Verilog module name - configuration_parse_and_encapsulate_taux_table
// Version: V4.0.20221216
// Created:
//         by - fenglin
////////////////////////////////////////////////////////////////////////////
// Description:
//        configuration_parse_and_encapsulate test aux
///////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps

module configuration_parse_and_encapsulate_taux_table
(
		i_clk,
		i_rst_n,
		
		iv_command       ,
        i_command_wr     ,        
        ov_command_ack   ,
        o_command_ack_wr ,

		ov_ram_addr ,
		ov_ram_wdata,
		o_ram_wr    ,
		iv_ram_rdata,
		o_ram_rd    
);

input 				i_clk;
input				i_rst_n;
input		[63:0]	iv_command;		
input				i_command_wr;
output	reg	[63:0]	ov_command_ack;
output	reg			o_command_ack_wr;

output	reg	[3:0]   ov_ram_addr   ;   
output	reg	[14:0]  ov_ram_wdata  ;   
output	reg	        o_ram_wr      ;      
input	 	[14:0]  iv_ram_rdata  ;   
output	reg	        o_ram_rd      ;


always@(posedge i_clk or negedge i_rst_n) begin
	if(! i_rst_n) begin		
		ov_ram_addr		        <= 4'b0;
		ov_ram_wdata	        <= 15'b0;
		o_ram_wr               	<= 1'b0;
		o_ram_rd               	<= 1'b0;
	end
	else begin
		if (i_command_wr == 1'b1) begin
			if(iv_command[63:62] == 2'h0)begin //configure DIT module
				if((iv_command[50:32]>19'd15)&&(iv_command[50:32]<19'd32))begin
				    ov_ram_addr      <= iv_command[35:32];
					ov_ram_wdata     <= iv_command[14:0] ;
					o_ram_wr         <= 1'b1 ;
					o_ram_rd         <= 1'b0 ;
				end
				else begin
					ov_ram_addr      <= 4'b0 ;
					ov_ram_wdata     <= 15'b0;
					o_ram_wr         <= 1'b0 ;
					o_ram_rd         <= 1'b0 ;
				end 						
			end
			else if(iv_command[63:62] == 2'h2) begin //read
				if((iv_command[50:32]>19'd15)&&(iv_command[50:32]<19'd32))begin
				    ov_ram_addr      <= iv_command[35:32];
					ov_ram_wdata     <= 15'b0 ;
					o_ram_wr         <= 1'b0 ;
					o_ram_rd         <= 1'b1 ;
				end
				else begin
					ov_ram_addr      <= 4'b0 ;
					ov_ram_wdata     <= 15'b0;
					o_ram_wr         <= 1'b0 ;
					o_ram_rd         <= 1'b0 ;
				end 						
			end
			else begin
				ov_ram_addr      <= 4'b0 ;
				ov_ram_wdata     <= 15'b0;
				o_ram_wr         <= 1'b0 ;
				o_ram_rd         <= 1'b0 ;
			end
		end
		else begin
			ov_ram_addr      <= 4'b0 ;
			ov_ram_wdata     <= 15'b0;
			o_ram_wr         <= 1'b0 ;
			o_ram_rd         <= 1'b0 ;
		end
	end
end

reg  [2:0]  rv_ram_rden;
reg  [3:0]  rv_ram_raddr0;
reg  [3:0]  rv_ram_raddr1;
reg  [3:0]  rv_ram_raddr2;
always@(posedge i_clk or negedge i_rst_n)begin
    if(!i_rst_n) begin
        rv_ram_rden   <= 3'b0;
        rv_ram_raddr0 <= 5'b0;
        rv_ram_raddr1 <= 5'b0;
        rv_ram_raddr2 <= 5'b0;
    end
    else begin
        rv_ram_rden   <= {rv_ram_rden[1:0],o_ram_rd};
        rv_ram_raddr0 <= ov_ram_addr;
        rv_ram_raddr1 <= rv_ram_raddr0;
        rv_ram_raddr2 <= rv_ram_raddr1;        
    end
end

always@(posedge i_clk or negedge i_rst_n)begin
    if(!i_rst_n) begin
        o_command_ack_wr      <= 1'b0    ;
        ov_command_ack        <= 64'b0   ;
    end
    else begin
        if(rv_ram_rden[2])begin//get data from ram
            o_command_ack_wr      <= 1'b1                  ;
			ov_command_ack[63:61] <= 3'b110;//iv_command[63:61]
			ov_command_ack[60:32] <= {27'h1,rv_ram_raddr2};			
            ov_command_ack [31:0] <= {17'b0,iv_ram_rdata}  ;         
        end
        else begin
            o_command_ack_wr      <= 1'b0    ;
            ov_command_ack        <= 64'b0    ;
        end        
    end
end       
endmodule
